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HT48R064 Datasheet(PDF) 53 Page - Holtek Semiconductor Inc |
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HT48R064 Datasheet(HTML) 53 Page - Holtek Semiconductor Inc |
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53 / 94 page ![]() HT48R063/064/065/066/0662/067 Rev. 1.30 53 June 11, 2010 When an interrupt request is generated it takes 2 or 3 in- struction cycle before the program jumps to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request then it will take 3 cy- cles before the program jumps to the interrupt vector. Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. HT48R063/064/065 Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter 0 Overflow 2 08H Time Base Overflow 3 0CH HT48R066 Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter 0 Overflow 2 08H Timer/Event Counter 1 Overflow 3 0CH Time Base Overflow 4 10H HT48R0662 Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter 0 Overflow 2 08H Timer/Event Counter 1 Overflow 3 0CH ¾¾ 10H Time Base Overflow 4 14H HT48R067 Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter 0 Overflow 2 08H Timer/Event Counter 1 Overflow 3 0CH Timer/Event Counter 2 Overflow 4 10H ¾¾ 14H Time Base Overflow 5 18H In cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. Wait for 2 ~ 3 Instruction Cycles Main Program ISR Entry Enable Bit Set ? Main Program RETI (it will set EMI automatically) Automatically Disable Interrupt Clear EMI & Request Flag Interrupt Request or Interrupt Flag Set by Instruction Y N Interrupt Flow |
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