HT6220A/HT6221A/HT6221B/HT6222A

Rev. 1.10

5

June 1, 2010

The output code carrier of the DOUT pin is shown in Timing 2.

The transmission codes employ the PPM (Pulse Position Modulation) method to represent their two logic states by

²0²

(1.12ms) and

²1² (2.24ms) as shown in Timing 3.

C a r r i e r

2 6 . 3 m s

8 . 7 7 m s

3 8 k H z

Timing 2. 38kHz Carrier

The algorithm rule of the address codes (A0~A15) can

be selected by mask option.

In this case, the 16-bit on-chip MASK ROM (ROM1

and ROM2) are available, and the value of ROM1 (8

bits) and ROM2 (8 bits) are decided by one MASK

LAYER. The current value of ROM1 and ROM2 are

both

²00H². The A0~A7 are set by logical OR between

the external switch S0~S7 and the ROM1. The

A8~A15 equal some bits inverted to A0~A7, the inver-

sion are decided by Logical OR between the external

switch S8~S15 and the ROM2.

For example:

The following is an illustration of these rules in selecting

the address codes (A0~A15).

" O n e "

" Z e r o "

d a t a p e r i o d ( 1 . 1 2 m s )

d a t a p e r i o d ( 2 . 2 4 m s )

3 8 k H z c a r r i e r

3 8 k H z c a r r i e r

0 . 5 6 m s

Timing 3. Logic States

H T 6 2 2 0 A

A I N

S 8

S 3

S 2

S 1

S 0

S 9

S 1 0

S 1 1

C 1

C 2

C 3

C 4

( S w i t c h O p e n : 0 , S w i t c h C l o s e : 1 )

1

0

0

0

0

0

0

0

C o m p l e m e n t

1 : n o n i n v e r s i o n

0 : i n v e r s i o n

S 0 ~ S 4 O R R O M 1

S 8 ~ S 1 2 O R R O M 2

1

0

1

0

0

0

0

0

1

1

0

1

1

1

1

1

E x t e r n a l S w i t c h S 0 ~ S 7 :

O n - c h i p R O M 1 , R O M 2 :

A 0 ~ A 7 :

A 8 ' ~ A 1 5 ' :

A 8 ~ A 1 5 :

b i t 0

b i t 7

b i t 0

b i t 7

S 0

S 1

S 2 S 3

S 8 S 9 S 1 0 S 1 1

F i l l w i t h z e r o a u t o m a t i c a l l y

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

1

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1 N 4 1 4 8 ´ 5

S 4

S 1 2

C 5

2 0 0 k W ´ 5

S 4

S 1 2