PIC24F04KA201 datasheet(27/224 Pages) MICROCHIP

27 / 224 page

Preliminary

DS39937B-page 25

PIC24F04KA201 FAMILY

4.0

MEMORY ORGANIZATION

As with Harvard architecture devices, the PIC24F

microcontrollers feature separate program and data

memory space and busing. This architecture also

allows the direct access of program memory from the

data space during code execution.

4.1

Program Address Space

The program address memory space of the PIC24F

devices is 4M instructions. The space is addressable by

a 24-bit value derived from either the 23-bit Program

Counter (PC) during program execution, or from a table

operation or data space remapping, as described in

Section 4.3 “Interfacing Program and Data Memory

Spaces”

The user access to the program memory space is

restricted to the lower half of the address range

(000000h to 7FFFFFh). The exception is the use of

TBLRD/TBLWT

operations, which use TBLPAG<7> to

permit access to the Configuration bits and Device ID

sections of the configuration memory space.

The memory map for the PIC24F04KA201 family of

devices is displayed in Figure 4-1.

FIGURE 4-1:

PROGRAM SPACE

MEMORY MAP FOR

PIC24F04KA201 FAMILY

DEVICES

Note:

Memory areas are not displayed to scale.

Reset Address

DEVID (2)

GOTO

Instruction

Reserved

Interrupt Vector Table

PIC24F04KA200/201

Device Config Registers

Reserved

Unimplemented

Read ‘0’

Flash

Program Memory

(1408 instructions)

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