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PIC24F04KA201 Datasheet(PDF) 37 Page - Microchip Technology |
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PIC24F04KA201 Datasheet(HTML) 37 Page - Microchip Technology |
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37 / 224 page  TABLE 4-17: DUAL COMPARATOR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CMSTAT 0630 CMSIDL — — — — — C2EVT C1EVT — — — — — — C2OUT C1OUT 0000 CVRCON 0632 — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 CM1CON 0634 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 —CREF — — CCH1 CCH0 0000 CM2CON 0636 CON COE CPOL CLPWR — — CEVT COUT EVPOL1 EVPOL0 —CREF — — CCH1 CCH0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: CLOCK CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RCON 0740 TRAPR IOPUWR SBOREN — — DPSLP — PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1) OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK — LOCK —CF — SOSCEN OSWEN (Note 2) CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — 3140 OSCTUN 0748 — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 REFOCON 074E ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000 HLVDCON 0756 HLVDEN —HLSIDL — — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: RCON register Reset values are dependent on type of Reset. 2: OSCCON register Reset values are dependent on configuration fuses and by type of Reset. TABLE 4-19: DEEP SLEEP REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets(1) DSCON 0758 DSEN — — — — — — — — — — — — — DSBOR RELEASE 0000 DSWSRC 075A — — — — — — —DSINT0 DSFLT — —DSWDT —DSMCLR — DSPOR 0000 DSGPR0 075C Deep Sleep General Purpose Register 0 0000 DSGPR1 075E Deep Sleep General Purpose Register 1 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: The Deep Sleep registers are only reset on a VDD POR event. |
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