PIC24F04KA201 datasheet(42/224 Pages) MICROCHIP

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PIC24F04KA201 FAMILY

DS39937B-page 40

Preliminary

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

4.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into an 8K word page (in PIC24F08KA1XX

devices) and a 16K word page (in PIC24F16KA1XX

devices) of the program space. This provides

transparent access of stored constant data from the

data space without the need to use special instructions

(i.e., TBLRDL/H).

Program space access through the data space occurs

if the MSb of the data space EA is ‘1’, and PSV is

enabled by setting the PSV bit in the CPU Control

(CORCON<2>) register. The location of the program

memory space to be mapped into the data space is

determined by the Program Space Visibility Page

Address register (PSVPAG). This 8-bit register defines

any one of 256 possible pages of 16K words in pro-

gram space. In effect, PSVPAG functions as the upper

8 bits of the program memory address, with the 15 bits

of the EA functioning as the lower bits.

By incrementing the PC by 2 for each program memory

word, the lower 15 bits of data space addresses directly

map to the lower 15 bits in the corresponding program

space addresses.

Data reads from this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111

1111

’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV, which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

00000000

‘Phantom’ Byte

TBLRDH.B

(Wn<0> = 0)

TBLRDL.W

TBLRDL.B

(Wn<0> = 1)

TBLRDL.B

(Wn<0> = 0)

TBLPAG

000000h

800000h

002BFEh

Program Space

Data EA<15:0>

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register. Only read

operations are provided; write operations are also valid in the

user memory area.

Note:

PSV access is temporarily disabled during

table reads/writes.

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