TS5A3159

1 W SPDT ANALOG SWITCH

SCDS174B − AUGUST 2004 – REVISED MAY 2005

www.ti.com

2

ORDERING INFORMATION

TA

PACKAGE(1)

ORDERABLE PART NUMBER

TOP-SIDE MARKING(2)

−40

°C to 85°C

SOT (SOT-23) − DBV

Tape and reel

TS5A3159DBVR

JA8_

−40

°C to 85°C

SOT (SC-70) − DCK(2)

Tape and reel

TS5A3159DCKR

JA_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V+

Supply voltage range(2)

−0.5

6.5

V

VNO, VCOM

Analog voltage range(2)(3)(4)

−0.5

V+ + 0.5

V

II/OK

Analog port diode current

VNO, VCOM < 0 or VNO, VCOM > V+

±50

mA

INO, ICOM

ON−state switch current

VNO, VCOM = 0 to V+

±200

mA

ON−state peak switch current(5)

±400

mA

VIN

Digital input voltage range(2)(3)

−0.5

6.5

V

IIK

Digital input clamp current

VIN < 0

−50

mA

Continuous current through V+ or GND

±100

mA

θJA

Package thermal impedance(6)

165

°C

Tstg

Storage temperature range

−65

150

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(4) This value is limited to 5.5 V maximum.

(5) Pulse at 1 ms duration < 10% duty cycle.

(6) The package thermal impedance is calculated in accordance with JESD 51-7.