56F807 datasheet(38/60 Pages) FREESCALE

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56F807 Technical Data Technical Data, Rev. 16

Freescale Semiconductor

3.7 Serial Peripheral Interface (SPI) Timing

Table 3-12 SPI Timing1

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

—

3-19-3-22

Enable lead time

Master

Slave

tELD

—

3-22

Enable lag time

Master

Slave

tELG

—

100

—

3-22

Clock (SCK) high time

Master

Slave

tCH

17.6

12.5

—

3-19, 3-20, 3-21,

3-22

Clock (SCK) low time

Master

Slave

tCL

24.1

—

3-22

Data set-up time required for inputs

Master

Slave

tDS

—

3-19, 3-20, 3-21,

3-22

Data hold time required for inputs

Master

Slave

tDH

—

3-19, 3-20, 3-21,

3-22

Access time (time to data active from

high-impedance state)

Slave

4.8

3-22

Disable time (hold time to high-impedance state)

Slave

3.7

15.2

3-22

Data Valid for outputs

Master

Slave (after enable edge)

tDV

—

4.5

20.4

3-19, 3-20, 3-21,

3-22

Data invalid

Master

Slave

tDI

—

3-19, 3-20, 3-21,

3-22

Rise time

Master

Slave

—

11.5

10.0

3-19, 3-20, 3-21,

3-22

Fall time

Master

Slave

—

9.7

9.0

3-19, 3-20, 3-21,

3-22

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