68HC05CT4 datasheet(73/142 Pages) FREESCALE

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Synchronous Serial Interface (SSI)

SSI Registers

MC68HC05CT4 — Rev. 2.0

General Release Specification

Synchronous Serial Interface (SSI)

being enabled. Always disable the SSI first, by clearing the SE bit, before

altering these control bits within the SSI control register (SCR).

SIE — SSI Interrupt Enable

This bit determines whether an interrupt request should be generated

when a transfer is complete.

When set, an interrupt request is made if the CPU is in the run or wait

mode of operation and status flag bit SF is set.

When cleared, no interrupt requests are made by the SSI.

SE — SSI Enable

When set, this bit enables the SSI, makes PD5 the SCK pin, and

makes PD4 the SDIO pin.

When SE is cleared, any transmission in progress is aborted, the bit

counter is reset, and pins SCK and SDIO revert to being PD5 and

PD4.

LSBF — Least Significant Bit (LSB)First

When set, data is sent and received in a least significant bit (LSB) first

format.

When cleared, data is sent and received in a most significant bit

(MSB) first format.

MSTR — Master Mode

When set, this bit configures the SSI to the master mode. This means

that the transmission is initiated by a write to the data register and the

SCK pin becomes an output providing a synchronous data clock at a

rate determined by the SR bits.

Address:

$001E

Bit 7

654321

Bit 0

Read:

SIE

LSBF

MSTR

CPOL

T/R

SR1

SR0

Write:

Reset:

00001000

Figure 9-3. SSI Control Register (SCR)

Freescale Semiconductor, Inc.

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