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MAC7200 Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 144 Page - Freescale Semiconductor, Inc |
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144 / 976 page ![]() Clock Generation MAC7200 Microcontroller Family Reference Manual, Rev. 2 66 Freescale Semiconductor Figure 5-6. External Clock 1:1 Mode Clock Path 5.2.1.4 External Clock PLL Mode In this mode, the system clock is fed from an external 3.3V clock, and the PLL is enabled. Refer to Figure 5-7. XCLKS = 0 PLLSEL = 1 (PLL is not bypassed) Eqn. 5-7 Eqn. 5-8 OSC EXTAL OSCCLK 0 1 XTAL PLL PLLSEL PLLCLK System Clock CRG ÷2 Peripheral Bus Clock SystemClock PLLCLK =2 OSCCLK SYNR 1 + REFDV 1 + ------------------------------ × × = PeripheralBusClock SystemClock 2 ----------------------------------- PLLCLK 2 ------------------------ == |
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