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MAC7200 Datasheet(PDF) 146 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 146 Page - Freescale Semiconductor, Inc |
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146 / 976 page ![]() Clock Gating MAC7200 Microcontroller Family Reference Manual, Rev. 2 68 Freescale Semiconductor 5.4 Clock Gating On the MAC72xx, there are two levels of clock gating implemented: Table 5-3. Module Clock Usage Overview Module/Pin System Clock (Fast Clock) Peripheral Bus Clock (Slow Clock) Oscillator Clock ARM7 Core X AXBS X FlexBus X CLKOUT X Nexus X SRAM X INTC X MCM (except SWT) X SWT (in MCM) X1 1. PLLCLK is selected when the device is in Self Clock Mode (SCM). X1 DMA2 X AIPS X Flash (array interface) X Flash (registers) X DMA_CH_MUX X IIC X eSCI_A/B X SPI_A/B/C X SSM X PIT (except RTI) X RTI (in PIT) X1 X1 FlexCAN_A/B X2 2. Can be switched between the Peripheral Bus Clock and Oscillator Clock via the CLK_SRC bit in the CTRL register in the corresponding FlexCAN. X2 ATD_A X eMIOS X PIM X CRG X PTI X BAM X |
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