MAC7200 datasheet(164/976 Pages) FREESCALE

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Interrupts

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

7.3.1

Interrupt Clearing

By definition, all interrupt flags that can be cleared by accessing an interrupt status bit should be cleared

by writing ‘1’. Clear on read, or clear on write 0 are not allowed on the MAC72xx device. All interrupts

sources have been checked, and meet this requirement. The obvious exception are the external interrupts

XIRQ, IRQ and NMI.

7.3.2

XIRQ and IRQ

Please also see Section 7.3.4, “Non-Maskable Interrupt (NMI)” for details on the NMI, and the behaviour

of the XIRQ interrupt pin when in NMI mode.

7.3.3

PIT RTI and Timer 4

The PIT Timer 4 and RTI interrupts are OR’d together in order to allow maximum flexibility in PIT

interrupt generation. Combined with the fact that the Timer 4 and RTI interrupts can be masked

independently, this enables the following use cases:

•

Mask RTI and unmask Timer 4: Timer 4 will generate the interrupt

•

Mask Timer 4 and unmask RTI: RTI will generate the interrupt

•

Unmask both: Timer 4 or RTI will generate the interrupt

•

Mask both: no interrupts generated

7.3.4

Non-Maskable Interrupt (NMI)

The actual implementation of the NMI on the MAC72xx is done almost completely within the MCM

module. The NMI has the following features:

•

Write-once enabling of NMI mode in order to improve fault tolerance

•

Write-once selectable NMI polarity in order to improve fault tolerance

•

NMI Pending status

Because the IRQ and FIRQ interrupts may be masked by software in the ARM7 core, and modification to

the ARM7 core was not deemed acceptable, an alternative method for implementing the NMI was

conceived. The ARM7 core exceptions look like:

Table 7-3. ARM7 Core Exception

Priority

Exception

Software Maskable ?

Highest

RESET

Data Abort

3FIRQ

Yes

4IRQ

Yes

Pre-fetch Abort

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