MAC7200 datasheet(165/976 Pages) FREESCALE

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Interrupts

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

There are several requirements for the NMI on the MAC72xx:

•

NMI is re-entrant

•

Minimize NMI latency

•

Automatic disabling of IRQ/FIRQ during NMI handling with the possibility of explicit software

re-enable

•

NMI has priority in the case of simultaneous NMI/Pre-fetch abort

The Data Abort exception has a higher priority in the core than the Instruction Abort, but since the NMI

must be associated with a bus access, the interrupt latency can be improved by associating it with

instruction fetches, which are far more frequent. This means that a normal Data Abort will have higher

priority than an NMI, which may not be desirable.

To implement a "truer" NMI, the abort could be forced, regardless of the access type (instruction or data).

This would place more burden on the customer, in that they would have to check for NMIs in both the

Instruction and Data Abort exception routines, but this would give us a statistically better latency at least.

However, even with this scheme, there is no guaranteed latency. Due to the nature of the ARM instruction

set (i.e.-almost all instructions can be made conditional), a handshaking scheme should be implemented

that tags every bus access with an NMI-caused abort until the user services the NMI. It may be tricky to

avoid re-entrancy of the Data Abort routine with this scheme.

The sequence of events in the system looks like the following:

1. System resets in non-NMI mode

2. Software puts the SoC put into NMI mode and sets NMI polarity by writing a write-once register

in the MCM. Until this happens the NMI interrupts are disabled, regardless of the value of the

ipi_nmi input.

3. Once NMI mode is entered, the SoC forces proper sensitization of the path from ipp_ind (pad

PD3) to the ipp_nmi input on the platform.

4. When a change from passive to active is seen on ipi_nmi (i.e.-edge sensitive), the MCM performs

the following actions:

— Set the NMI Pending bit in the MCM

— Drive the FIRQ/IRQ inputs to the core negated

— Begin tagging all instruction fetches as aborted

5. When one of the tagged instructions enters the execute phase in the ARM7 pipeline, a Pre-fetch

abort exception is taken (assuming no higher exception occurs at the same time).

6. Upon seeing the instruction fetch to $0000_000C (Pre-fetch abort), the MCM stops tagging the

instructions.

7. The ISR saves off all registers (i.e.-switch context, PC, PSR, etc.)

Undefined Instruction

Lowest

SWI

Yes

Table 7-3. ARM7 Core Exception (Continued)

Priority

Exception

Software Maskable ?

MAC7200 Datasheet(PDF) 165 Page - Freescale Semiconductor, Inc

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