MAC7200 datasheet(166/976 Pages) FREESCALE

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Interrupts

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

8. The ISR reads the NMI pending bit to determine if the exception was due to an NMI or to a real

Pre-fetch abort. This provides the simplest (i.e.-lowest latency) NMI recognition, as well as

providing for the case where a simultaneous NMI and Pre-fetch abort occur. In this case, the NMI

should be serviced first (because the ISR sees a pending NMI). Once the NMI ISR is completed,

the ARM core will try to re-fetch the "offending" instruction, so any "real" Pre-fetch aborts will be

taken again.

9. Once the NMI branch of the ISR is taken, the ISR can set or clear the F and I bits in the CPSR to

determine if a FIRQ/IRQ exception should be allowed during execution of the NMI handler.

Remember, during this time, the FIRQ/IRQ signals to the ARM core are being forced negated by

the MCM

10. Next, the ISR should write ’1’ to the NMI Pending bit. This will cause the MCM to do 2 things:

— Stop forcing the FIRQ/IRQ negated, thereby enabling/disabling the FIRQ/ IRQ based solely on

the F/I bits in the CPSR

— Enable another NMI (i.e.-re-entrant NMI). This is automatic, since the NMI input is edge

sensitive (i.e.-you must negate it by clearing the source before it can be asserted again).

11. Once the NMI input is negated, another active edge of the NMI will trigger a new NMI exception,

if the NMI pending bit was written ‘1’ (i.e.-Step #10). If NMI re-entrancy is not desired, the NMI

pending bit can be written at the end of the exception handler.

Since the Data Abort exception has higher priority than the Pre-fetch abort, the Data Abort exception

handler may be entered while an NMI is pending. Since the Data Abort is not tagged for a pending NMI,

and Data Aborts received are true Data Aborts. Upon entering the Data Abort exception, the first

instruction fetch is tagged by the NMI hardware, and the Pre-fetch Abort exception handler will be called,

thus guaranteeing higher NMI priority with a small latency penalty.

When the device is in NMI mode, pin PD[3] is used exclusively for the NMI. As such, the following

special behavior is in effect:

•

The XIRQ interrupt input to the platform is driven low (disabled)

•

The port control signals from the PIM are ignored, so that the pad is always configured to be an

input.

MAC7200 Datasheet(PDF) 166 Page - Freescale Semiconductor, Inc