PC912XDP512F0CALR datasheet(76/1348 Pages) FREESCALE

76 / 1348 page

Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1.6.2

Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the

respective module Block Guides for register reset states.

1.6.2.1

I/O Pins

Refer to the PIM Block Guide for reset conﬁgurations of all peripheral module ports.

1.6.2.2

Memory

The RAM array is not initialized out of reset.

1.7

COP Conﬁguration

The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge

of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See

Table 1-13 and Table 1-14 for coding. The FCTL register is loaded from the Flash conﬁguration ﬁeld byte

at global address $7FFF0E during the reset sequence

NOTE

If the MCU is secured the COP timeout rate is always set to the longest

period (CR[2:0] = 111) after COP reset.

Table 1-13. Initial COP Rate Conﬁguration

NV[2:0] in

FCTL Register

CR[2:0] in

COPCTL Register

000

111

001

110

010

101

011

100

011

101

010

110

001

111

000

Table 1-14. Initial WCOP Conﬁguration

NV[3] in

FCTL Register

WCOP in

COPCTL Register

PC912XDP512F0CALR Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

PC912XDP512F0CALR Datasheet(HTML) 76 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL