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MSP430F5437AIPN Datasheet(PDF) 39 Page - Texas Instruments |
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MSP430F5437AIPN Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 99 page  MSP430F543x, MSP430F541x www.ti.com SLAS612C – AUGUST 2009 – REVISED MARCH 2010 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) Voltage VCC applied at supply pins DVCC/AVCC to supply pins DVSS/AVSS –0.3 V to 4.1 V Voltage applied to any pin (excluding VCORE)(2) –0.3 V to VCC + 0.3 V Diode current at any device pin ±2 mA Storage temperature range(3), Tstg –55°C to 105°C Maximum junction temperature, TJ 95°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Thermal Packaging Characteristics VALUE UNIT QFP (PZ) 50.1 Low-K board (JESD51-3) QFP (PN) 57.9 qJA Junction-to-ambient thermal resistance, still air °C/W QFP (PZ) 40.8 High-K board (JESD51-7) QFP (PN) 37.9 QFP (PZ) 8.9 qJC Junction-to-case thermal resistance °C/W QFP (PN) 10.3 Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage during program execution and flash programming VCC 2.2 3.6 V (VCC = DVCC1/2/3/4 = AVCC) (1) VSS Supply voltage (VSS = DVSS1/2/3/4 = DVSS= AVSS) 0 V TA Operating free-air temperature I version –40 85 °C TJ Operating junction temperature I version –40 85 °C CVCORE Recommended capacitor at VCORE 470 nF CDVCC/ Capacitor ratio of DVCC to VCORE 10 CVCORE PMMCOREVx = 2, fSYSTEM Processor frequency (maximum MCLK frequency)(2) (3) (see Figure 1) 0 18.0 MHz 2.2 V ≤ VCC ≤ 3.6 V (1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. (2) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. (3) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 39 |
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