TMS320DM6467 datasheet(13/357 Pages) TI

13 / 357 page

3.3.5

Tightly Coupled Memory (TCM)

3.3.6

Advanced High-Performance Bus (AHB)

3.3.7

Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

3.3.8

ARM Memory Mapping

3.3.8.1 ARM Internal Memories

3.3.8.2 External Memories

TMS320DM6467

Digital Media System-on-Chip

www.ti.com

SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt

Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM

and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides

for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the

D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be

stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM

sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to

the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to

the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the

instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. The instruction

region at 0x0000 and data region at 0x10000 map to the same physical 32-KB TCM RAM. Placing the

instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,

as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB

each, which allows simultaneous instruction and data accesses to be accomplished if the code and data

are in separate banks.

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and

the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the

Config Bus and the external memories bus.

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an

Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6467 also includes the

Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The DM6467 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.

The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured

trace data.

The ARM memory map is shown in Section 3.5, Memory Map Summary of this document. The ARM has

access to memories shown in the following sections.

The ARM has access to the following ARM internal memories:

• 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow

simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data

(D-TCM) to the different memory regions.

• 8KB ARM Internal ROM

The ARM has access to the following external memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash / NAND Flash

• ATA

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