TMS320DM6467 datasheet(2/357 Pages) TI

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TMS320DM6467

Digital Media System-on-Chip

SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009

www.ti.com

• External Memory Interfaces (EMIFs)

• One Serial Peripheral Interface (SPI) With Two

–

32-Bit DDR2 SDRAM Memory Controller

Chip-Selects

With 512M-Byte Address Space (1.8-V I/O)

• Master/Slave Inter-Integrated Circuit (I2C

–

Asynchronous16-Bit Wide EMIF (EMIFA)

Bus™)

With 128M-Byte Address Reach

• Two Multichannel Audio Serial Ports (McASPs)

• Flash Memory Interfaces

–

One Four Serializer Transmit/Receive Port

–

NOR (8-/16-Bit-Wide Data)

–

One Single DIT Transmit Port for S/PDIF

–

NAND (8-/16-Bit-Wide Data)

• 32-Bit Host Port Interface (HPI)

• Enhanced Direct-Memory-Access (EDMA)

• VLYNQ™ Interface (FPGA Interface)

Controller (64 Independent Channels)

• Two Pulse Width Modulator (PWM) Outputs

–

Programmable Default Burst Size

• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)

• 10/100/1000 Mb/s Ethernet MAC (EMAC)

• Up to 33 General-Purpose I/O (GPIO) Pins

–

IEEE 802.3 Compliant (3.3-V I/O Only)

(Multiplexed With Other Device Functions)

–

Supports MII and GMII Media Independent

Interfaces

• On-Chip ARM ROM Bootloader (RBL)

–

Management Data I/O (MDIO) Module

• Individual Power-Saving Modes for ARM/DSP

• USB Port With Integrated 2.0 PHY

• Flexible PLL Clock Generators

–

USB 2.0 High-/Full-Speed Client

• IEEE-1149.1 (JTAG) Boundary-

–

USB 2.0 High-/Full-/Low-Speed Host

Scan-Compatible

(Mini-Host, Supporting One External

• 529-Pin Pb-Free BGA Package

Device)

(ZUT Suffix), 0.8-mm Ball Pitch

• 32-Bit, 33-MHz, 3.3 V Peripheral Component

• 0.09-µm/7-Level Cu Metal Process (CMOS)

Interconnect (PCI) Master/Slave Interface

• 3.3-V and 1.8-V I/O, 1.2-/1.05-V Internal

–

Conforms to PCI Specification 2.3

• Applications:

• Two 64-Bit General-Purpose Timers (Each

–

Video Encode/Decode/Transcode/Transrate

Configurable as Two 32-Bit Timers)

–

Digital Media

• One 64-Bit Watch Dog Timer

–

Networked Media Encode/Decode

• Three Configurable UART/IrDA/CIR Modules

–

Video Imaging

(One With Modem Control Signals)

–

Video Infrastructure

–

Supports up to 1.8432 Mbps UART

–

Video Conferencing

–

SIR and MIR (0.576 MBAUD)

–

CIR With Programmable Data Encoding

Digital Media System-on-Chip (DMSoC)

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