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DM3725CBC100 Datasheet(PDF) 33 Page - Texas Instruments

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Part # DM3725CBC100
Description  Applications Processor
PDF  268 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725CBC100 Datasheet(HTML) 33 Page - Texas Instruments

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DM3730, DM3725
www.ti.com
SPRS685 – AUGUST 2010
Table 2-1. Ball Characteristics (CBP Pkg.)(3) (continued)
BALL
BUFFER
BALL
BALL
RESET
PULLUP
BALL TOP
RESET
STRENG
IO CELL
BOTTOM
PIN NAME [3]
MODE [4]
TYPE [5]
RESET
REL. MODE POWER [9] HYS [10]
/DOWN
[2]
REL.
TH (mA)
[13]
[1]
STATE [6]
[8]
TYPE [12]
STATE [7]
[11]
AH3
NA
mmc2_dat5
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_dir_dat1
1
O
cam_global_reset
2
IO
mmc3_dat1
3
IO
gpio_137
4
IO
mm3_rxdp
6
IO
safe_mode
7
AF3
NA
mmc2_dat6
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_dir_cmd
1
O
cam_shutter
2
O
mmc3_dat2
3
IO
gpio_138
4
IO
safe_mode
7
AE3
NA
mmc2_dat7
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_clkin
1
I
mmc3_dat3
3
IO
gpio_139
4
IO
mm3_rxdm
6
IO
safe_mode
7
AF6
NA
mcbsp3_dx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_cts
1
I
gpio_140
4
IO
safe_mode
7
AE6
NA
mcbsp3_dr
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_rts
1
O
gpio_141
4
IO
safe_mode
7
AF5
NA
mcbsp3_clkx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_tx
1
O
gpio_142
4
IO
safe_mode
7
AE5
NA
mcbsp3_fsx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart2_rx
1
I
gpio_143
4
IO
safe_mode
7
AB26
NA
uart2_cts
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dx
1
IO
gpt_9_pwm_evt
2
IO
gpio_144
4
IO
safe_mode
7
AB25
NA
uart2_rts
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_dr
1
I
gpt_10_pwm_evt
2
IO
gpio_145
4
IO
safe_mode
7
AA25
NA
uart2_tx
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_clkx
1
IO
gpt_11_pwm_evt
2
IO
gpio_146
4
IO
safe_mode
7
AD25
NA
uart2_rx
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
mcbsp3_fsx
1
IO
gpt_8_pwm_evt
2
IO
gpio_147
4
IO
Copyright © 2010, Texas Instruments Incorporated
TERMINAL DESCRIPTION
33
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Product Folder Link(s): DM3730 DM3725



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