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DM3725CBC100 Datasheet(PDF) 1 Page - Texas Instruments |
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DM3725CBC100 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 268 page  DM3730, DM3725 www.ti.com SPRS685 – AUGUST 2010 DM3730, DM3725 Applications Processor Check for Samples: DM3730, DM3725 1 DM3730, DM3725 Applications Processor 1.1 Features 1234 • Additional C64x+TM Enhancements • DM3730/25 Applications Processor: – Protected Mode Operation – Compatible with OMAP™ 3 Architecture – Expectations Support for Error – MPU Subsystem Detection and Program Redirection • Up to 1-GHz ARM CortexTM-A8 Core – Hardware Support for Modulo Loop • NEON SIMD Coprocessor Operation – High Performance Image, Video, Audio – C64x+TM L1/L2 Memory Architecture (IVA2.2TM) Accelerator Subsystem • 32K-Byte L1P Program RAM/Cache • Up to 800-MHz TMS320C64x+TM DSP Core (Direct Mapped) • Enhanced Direct Memory Access (EDMA) • 80K-Byte L1D Data RAM/Cache (2-Way Controller (128 Independent Channels) Set- Associative) • Video Hardware Accelerators • 64K-Byte L2 Unified Mapped RAM/Cache – POWERVR SGX™ Graphics Accelerator (4- Way Set-Associative) (DM3730 only) • 32K-Byte L2 Shared SRAM and 16K-Byte • Tile Based Architecture Delivering up to L2 ROM 20 MPoly/sec – C64x+TM Instruction Set Features • Universal Scalable Shader Engine: • Byte-Addressable (8-/16-/32-/64-Bit Data) Multi-threaded Engine Incorporating Pixel • 8-Bit Overflow Protection and Vertex Shader Functionality • Bit-Field Extract, Set, Clear • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 • Normalization, Saturation, Bit-Counting • Fine Grained Task Switching, Load • Compact 16-Bit Instructions Balancing, and Power Management • Additional Instructions to Support • Programmable High Quality Image Complex Multiplies Anti-Aliasing – External Memory Interfaces: – Advanced Very-Long-Instruction-Word • SDRAM Controller (SDRC) (VLIW) TMS320C64x+TM DSP Core – 16, 32-bit Memory Controller With • Eight Highly Independent Functional 1G-Byte Total Address Space Units – Interfaces to Low-Power SDRAM • Six ALUs (32-/40-Bit); Each Supports – SDRAM Memory Scheduler (SMS) and Single 32- bit, Dual 16-bit, or Quad 8-bit, Rotation Engine Arithmetic per Clock Cycle • General Purpose Memory Controller • Two Multipliers Support Four 16 x 16-Bit (GPMC) Multiplies (32-Bit Results) per Clock – 16-bit Wide Multiplexed Address/Data Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Bus Results) per Clock Cycle – Up to 8 Chip Select Pins With • Load-Store Architecture With 128M-Byte Address Space per Chip Non-Aligned Support Select Pin • 64 32-Bit General-Purpose Registers – Glueless Interface to NOR Flash, • Instruction Packing Reduces Code Size NAND Flash (With ECC Hamming • All Instructions Conditional Code Calculation), SRAM and 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 POWERVR SGX is a trademark of Imagination Technologies Ltd. 3 OMAP is a trademark of Texas Instruments. 4 All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative Copyright © 2010, Texas Instruments Incorporated or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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