PIC18LF4331-ESLASHML datasheet(207/392 Pages) MICROCHIP

207 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 207

PIC18F2331/2431/4331/4431

SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER

R/W-0

WCOL

SSPOV(1)

SSPEN(2)

CKP

SSPM3(3)

SSPM2(3)

SSPM1(3)

SSPM0(3)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

WCOL:

Write Collision Detect bit

= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

bit 6

SSPOV

: Receive Overflow Indicator bit(1)

In SPI mode:

= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In

Master mode, the overflow bit is not set since each new reception (and transmission) is

initiated by writing to the SSPBUF register.

= No overflow

In I2C™ mode:

= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV

is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.

= No overflow

bit 5

SSPEN

: Synchronous Serial Port Enable bit(2)

In SPI mode:

= Enables serial port and configures SCK, SDO and SDI as serial port pins

= Disables serial port and configures these pins as I/O port pins

In I2C mode:

= Enables the serial port and configures the SDA and SCL pins as serial port pins

= Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4

CKP

: Clock Polarity Select bit

In SPI mode:

= Idle state for clock is a high level

= Idle state for clock is a low level

In I2C mode:

SCK release control.

= Enables clock

= Holds clock low (clock stretch). (Used to ensure data setup time.)

Note 1:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

When enabled, these pins must be properly configured as inputs or outputs.

Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

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