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PIC18LF4331-E/ML Datasheet(PDF) 211 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 211 Page - Microchip Technology |
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211 / 392 page ![]() 2010 Microchip Technology Inc. DS39616D-page 211 PIC18F2331/2431/4331/4431 FIGURE 19-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) TABLE 19-1: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 TRISC PORTC Data Direction Register 57 SSPBUF SSP Receive Buffer/Transmit Register 55 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 55 TRISA TRISA7(1) TRISA6(2) PORTA Data Direction Register 57 SSPSTAT SMP CKE D/A P S R/W UA BF 55 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. Note 1: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other oscillator modes. 2: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read ‘0’ in all other oscillator modes. SCK (CKP = 0) SDI (SMP = 0) SSPIF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCK (CKP = 1) SDO bit 7 bit 0 SS |
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