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P89V51RB2BBC Datasheet(PDF) 13 Page - NXP Semiconductors |
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P89V51RB2BBC Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 80 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx [1] Unimplemented bits in SFRs (labeled ’-’) are ‘X’s (unknown) at all times. Unless otherwise specified, ‘1’s should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read. SADDR Serial Port Address Register A9H SADEN Serial Port Address Enable B9H Bit address 87[1] 86[1] 85[1] 84[1] 83[1] 82[1] 81[1] 80[1] SPCTL SPI Control Register D5H SPIE SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SPCFG SPI Configuration Register AAH SPIF SPWCOL - - ---- SPDAT SPI Data 86H SP Stack Pointer 81H Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON* Timer Control Register 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit address CF CE CD CC CB CA C9 C8 T2CON* Timer2 Control Register C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 T2MOD Timer2 Mode Control C9H - - ENT2 T2OE DCEN TH0 Timer 0 HIGH 8CH TH1 Timer 1 HIGH 8DH TH2 Timer 2 HIGH CDH TL0 Timer 0 LOW 8AH TL1 Timer 1 LOW 8BH TL2 Timer 2 LOW CCH TMOD Timer 0 and 1 Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 WDTC Watchdog Timer Control C0H - - - WDOUT WDRE WDTS WDT SWDT WDTD Watchdog Timer Data/Reload 85H Table 4. Special function registers …continued * indicates SFRs that are bit addressable Name Description SFR address Bit functions and addresses MSB LSB |
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