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VSC056

Data Sheet

Revision 4.1

January 2008

3.2.81 B0h-B7h: Bit Control Port 3 (BCP30-BCP37)

These eight registers function the same as the Bit Control Port 0 registers except they provide individual bit

control for the Port 3 I/O pins. All register bits are identical from a control and status perspective, with the

only difference being the individual I/O pin controlled and the presence of the bypass function. The Data

Direction (bit 1) and General-Purpose Data (bit 0) bits are effectively the same bits found in the DDP0 and

GPD0 registers, with parallel read and write paths. Additionally, the control of the individual I/O pins

assigned to these registers can be overridden by the PBC0, PBC1, PBC2, and PBC3 registers when port

bypass control is required. For information about the functionality of the Bit Control Port 0 registers, see

“80h-87h: Bit Control Port 0 (BCP00-BCP07),” page 78.

The following table shows the bit assignments for the Bit Control Port 3 registers.

BCP30-BCP37

Address:

B0h-B7h

Reset Value:

0000_001Xb

Bit

Bit Label

Access

Description

PTE

R/W

Pulse Train Enable

This bit, along with the FS bits, enables one of eight pulse train circuits

controlled by the pulse train registers, PTC00 through PTC71 (70h through

7Fh), as the output drive function for this I/O pin.

When this bit is set, the FS bits select one of eight pulse train circuits instead of

the normal fixed-rate LED flashing circuits or the normal output drive mode. For

the various LED drive control modes, see Table 5, page 80.

After a reset or power on, this bit is cleared.

6:5

BYP1-0

R/W

Bypass Select

These two bits determine the bypass function of the odd-numbered I/O pins

P0.7, P0.5, P0.3, and P0.1.

Setting either or both of these bits causes the I/O pin to be configured as an

output that reflects the input state of the corresponding even-numbered I/O

pins P0.6, P0.4, P0.2, and P0.0.

As an example, P0.1 can be configured as an output that follows the signal

applied to the P0.0 input. These two register bits only appear in the

odd-numbered bit control registers BCP07, BCP05, BCP03, and BCP01. For

the available output drive combinations, see Table 4, page 80.

Note: These bits are only used when the bypass function is desired. They

should not be set when normal GPIO operation, PBC operation, or fan speed

monitoring are selected through the appropriate registers or through the use of

the FS, DD, and GPD bits. The PWM function (Port 0 only) and bypass function

are the highest priority controls for the appropriate I/O pin. The next highest

priorities are the PBC function (Port 3 through Port 6) and fan speed

monitoring (Port 1 and Port 2). The lowest priorities are the bit control features

found in the GPD, DD, and BCP registers.

Only one mode of operation should be enabled for each I/O pin at any time. If a

mode change is desired, first disable the existing mode, then enable the new

mode.

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