MB96310 datasheet(44/84 Pages) FUJITSU

44 / 84 page

DS07-13808-2E

MB96310 Series

2. Opposite phase external clock

• When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the

opposite phase to the X0 (X0A) pins.

Unused sub clock signal

If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A

pin and the X1A pin must be left open.

Notes on PLL clock mode operation

If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the

microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot

be guaranteed.

Power supply pins (VCC/VSS)

It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more

than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating

range.

VCC and VSS must be connected to the device from the power supply with lowest possible impedance.

As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1

μF between

VCC and VSS as close as possible to VCC and VSS pins.

Crystal oscillator and ceramic resonator circuit

Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors

with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and

ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins

with a ground area for stabilizing the operation.

It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator

manufacturer, especially when using low-Q resonators at higher frequencies.

Turn on sequence of power supply to A/D converter and analog inputs

It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after

turning the digital power supply (VCC) on.

It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this

case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously

on or off is acceptable).

Pin handling when not using the A/D converter

It is required to connect the unused pins of the A/D converter as AVCC = VCC

, AVSS = AVRH = AVRL = VSS.

10. Notes on Power-on

To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on

should be slower than 50

μs from 0.2 V to 2.7 V.

MB96310 Datasheet(PDF) 44 Page - fujitsu semiconductor