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MB96310 Datasheet(PDF) 63 Page - fujitsu semiconductor |
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MB96310 Datasheet(HTML) 63 Page - fujitsu semiconductor |
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63 / 84 page  MB96310 Series DS07-13808-2E 63 USART timing WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. Notes: • AC characteristic in CLK synchronized mode. • CL is the load capacity value of pins when testing. • Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”. • tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: •if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 •if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: (TA = -40°C to 125°C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition VCC = AVCC= 4.5V to 5.5V VCC = AVCC= 3.0V to 4.5V Unit Min Max Min Max Serial clock cycle time tSCYCI SCKn Internal Shift Clock Mode 4 tCLKP1 ⎯ 4 tCLKP1 ⎯ ns SCK ↓ → SOT delay time tSLOVI SCKn, SOTn -20 +20 -30 +30 ns SOT → SCK ↑ delay time tOVSHI SCKn, SOTn N*tCLKP1 - 20 *1 ⎯ N*tCLKP1 - 30 *1 ⎯ ns Valid SIN → SCK ↑ tIVSHI SCKn, SINn tCLKP1 + 45 ⎯ tCLKP1 + 55 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXI SCKn, SINn 0 ⎯ 0 ⎯ ns Serial clock “L” pulse width tSLSHE SCKn External Shift Clock Mode tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns Serial clock “H” pulse width tSHSLE SCKn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK ↓ → SOT delay time tSLOVE SCKn, SOTn ⎯ 2 tCLKP1 + 45 ⎯ 2 tCLKP1 + 55 ns Valid SIN → SCK ↑ tIVSHE SCKn, SINn tCLKP1/2 + 10 ⎯ tCLKP1/2 + 10 ⎯ ns SCK ↑ → Valid SIN hold time tSHIXE SCKn, SINn tCLKP1 + 10 ⎯ tCLKP1 + 10 ⎯ ns SCK fall time tFE SCKn ⎯ 20 ⎯ 20 ns SCK rise time tRE SCKn ⎯ 20 ⎯ 20 ns tSCYCI N 4*tCLKP1 2 5*tCLKP1, 6*tCLKP1 3 7*tCLKP1, 8*tCLKP1 4 ... ... |
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