L9951XP datasheet(27/36 Pages) STMICROELECTRONICS

27 / 36 page

L9951 / L9951XP

Functional description of the SPI

Doc ID 14173 Rev 8

27/36

OUT5 OC

recovery enable

In case of an over-current

event the over-current

status bit (status register

0) is set and the output is

switched off. If the over-

current recovery enable bit

is set the output will be

automatically reactivated

after a delay time resulting

in a PWM modulated

current with a

programmable duty cycle

(Bit 13 of Input data

Depending on occurrence

of overcurrent event and

internal clock phase it is

possible that one recovery

cycle is executed even if

this bit is set to zero.

Not ready bit

After switching the device

from standby mode to active

mode an internal timer is

started to allow charge pump

to settle before the outputs

can be activated. This bit is

cleared automatically after

start up time has finished.

Since this bit is controlled by

internal clock it can be used

for synchronizing testing

events(e.g. measuring filter

times).

OUT4 OC

recovery enable

Not used.

OUT3 OC

recovery enable

OUT5-HS

open-load

The open-load detection

monitors the load current in

each activated output stage. If

the load current is below the

open-load detection threshold

for at least 1 ms (tdOL) the

corresponding open-load bit

is set. Due to mechanical

/electrical inertia of typical

loads a short activation of the

outputs (e.g. 3ms) can be

used to test the open-load

status without changing the

mechanical/electrical state of

the loads.

OUT2 OC

recovery enable

OUT4-HS

open-load

OUT1 OC

recovery enable

OUT3-HS

open-load

OUT5 PWM

enable

If the PWM enable bit is

set and the output is

enabled (input register 0)

the output is switched on if

PWM input is high and

switched off if PWM input

is low.

OUT3-LS

open-load

OUT4 PWM

enable

OUT2-HS

open-load

OUT3 PWM

enable

OUT2-LS

open-load

OUT2 PWM

enable

OUT1-HS

open-load

OUT1 PWM

enable

OUT1-LS

open-load

No error bit

A logical NOR-combination of

all bits 1 to 14 in both status

registers. If bit 14 (Disable

Open-Load) is set, the open-

load status will be ignored

Table 20.

SPI - Input data and status register 1 (continued)

Input register 1 (write)

Status register 1 (read)

Bit

Name

Comment

Name

Comment

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