R29 datasheet(60/473 Pages) RENESAS

60 / 473 page

R8C/28 Group, R8C/29 Group

6. Voltage Detection Circuit

Rev.2.10

Sep 26, 2008

Page 41 of 441

REJ09B0279-0210

Figure 6.11

VW1C Register (J, K Version)

Voltage Monitor 1 Circuit Control Register

(1) (J, K Version)

Symbol

Address

After Reset(6)

VW1C

0036h

Bit Symbol

Bit Name

Function

NOTES:

The LVD1ON bit in the OFS register is

set to 1 and hardw are reset

: 0000X000b

Pow er-on reset, voltage monitor 1 reset

or LVD1ON bit in the OFS register is set

to 0, and hardw are reset

: 0100X001b

Set to 0.

b1 b0

b7 b6 b5 b4

VW1C0

Voltage monitor 1 reset

enable bit(4)

0 : Disable

1 : Enable

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

—

(b2)

Reserved bit

VW1C1

Voltage monitor 1 digital filter

disable mode select bit(2)

—

(b3)

Reserved bit

VW1F1

Sampling clock select bits

b5 b4

0 0 : fOCO-S divided by 1

0 1 : fOCO-S divided by 2

1 0 : fOCO-S divided by 4

1 1 : fOCO-S divided by 8

VW1F0

When read, the content is undefined.

VW1C6

Voltage monitor 1 circuit

mode select bit(3)

When the VW1C0 bit is 1(voltage monitor 1 reset

enabled), set to 1.

VW1C7

Voltage monitor 1 reset

generation condition select

bit(5, 7)

When the VW1C1 bit is 1(digital filter disabled

mode), set to 1.

When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or

below ). (Do not set to 0.)

Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.

To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting

The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 reset enabled).

The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).

Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).

Softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register.

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