R29 datasheet(102/473 Pages) RENESAS

102 / 473 page

R8C/28 Group, R8C/29 Group

10. Clock Generation Circuit

Rev.2.10

Sep 26, 2008

Page 83 of 441

REJ09B0279-0210

10.2

On-Chip Oscillator Clocks

These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip

oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.

10.2.1

Low-Speed On-Chip Oscillator Clock

The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,

peripheral function clock, fOCO, and fOCO-S.

After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as

the CPU clock.

If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed

on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.

The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating

ambient temperature. Application products must be designed with sufficient margin to allow for frequency

changes.

10.2.2

High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,

peripheral function clock, fOCO, fOCO-F, and fOCO40M.

To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO,

and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:

• All divide ratio mode settings are supported when VCC = 3.0 to 5.5 V

000b to 111b

(other than K version)

• Divide ratio of 4 or more when VCC = 2.7 to 5.5 V or K version

010b to 111b

• Divide ratio of 8 or more when VCC = 2.2 to 5.5 V (for N, D version only) 110b to 111b

After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is

started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can

be adjusted by registers FRA1 and FRA2.

The frequency correction data (the value is the same as that of the FRA1 register after a reset) corresponding to

the supply voltage ranges VCC = 2.7 to 5.5 V is stored in FRA4 register. Furthermore, the frequency correction

data corresponding to the supply voltage ranges VCC = 2.2 to 5.5 V is stored in FRA6 register (for N, D version

only). To use separate correction values to match these voltage ranges, transfer them from FRA4 or FRA6

The frequency correction data of 36.864 MHz is stored in the FRA7 register (for N, D version only). To set the

frequency of the high-speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7

bps to be 0% when the serial interface is used in UART mode (refer to Table 15.7 Bit Rate Setting Example in

UART Mode (Internal Clock Selected)).

Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make

adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the

high-speed on-chip oscillator clock will be 40 MHz or less.

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