P89LPC9211FDH datasheet(28/75 Pages) NXP

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P89LPC92X1

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Product data sheet

Rev. 2 — 1 December 2010

28 of 75

NXP Semiconductors

P89LPC9201/9211/922A1/9241/

8-bit microcontroller with 8-bit ADC

7.10 CCLK wake-up delay

The P89LPC9201/9211/922A1/9241/9251 has an internal wake-up timer that delays the

clock until it stabilizes depending on the clock source used. If the clock source is any of

the three crystal selections (low, medium and high frequencies) the delay is

1024 OSCCLK cycles plus 60

μsto100 μs. If the clock source is the internal RC

oscillator, the delay is 200

μs to 300 μs. If the clock source is watchdog oscillator or

external clock, the delay is 32 OSCCLK cycles.

7.11 CCLK modification: DIVM register

The OSCCLK frequency can be divided down up to 510 times by configuring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.12 Low power select

The P89LPC9201/9211/922A1/9241/9251 is designed to run at 18 MHz (CCLK)

maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be

set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0

allowing highest performance access. This bit can then be set in software if CCLK is

running at 8 MHz or slower.

Fig 8.

Block diagram of oscillator control

÷2

002aae428

RTC

ADC

(P89LPC9241/9251)

CPU

WDT

DIVM

CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RC OSCILLATOR

WITH CLOCK DOUBLER

WATCHDOG

OSCILLATOR

(7.3728 MHz/14.7456 MHz

± 1 %)

PCLK

RCCLK

(400 kHz

± 5 %)

P89LPC9211FDH Datasheet(PDF) 28 Page - NXP Semiconductors

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