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MM908E624ACEW/R2 Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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MM908E624ACEW/R2 Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 40 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 27 908E624 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES WINDOW WATCHDOG The window watchdog is configurable using an external resistor at the WDCONF terminal. The watchdog is cleared through by the MODE1:2 bits in the SPI Control register (refer to Table 8, page 29). A watchdog clear is only allowed in the open window. If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST_A terminal and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window. Figure 16. Window Watchdog Operation Watchdog Configuration If the WDCONF terminal is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDCONF terminal must be connected to GND. The watchdog period is calculated using the following formula: tPWD [ms] = 0.991 * REXT [kΩ] + 0.648 VOLTAGE REGULATOR The 908E624 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller. Current Limit (Over-current) Protection The voltage regulator has current limit to protect the device against over-current and short circuit conditions. Over-temperature Protection The voltage regulator also features an over-temperature protection having an over-temperature warning (Interrupt - VDDT) and an over-temperature shutdown. Stop Mode During Stop mode, the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode In Sleep mode the voltage regulator external VDD is turned off. FACTORY TRIMMING AND CALIBRATION To enhance the ease-of-use of the 908E624, various parameters (e.g., ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the “empty” (0xFF) state: • 0xFD80:0xFDDF Trim and Calibration Values • 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used. Trim Values The usage of the trim values, located in the flash memory, is explained in the following. Internal Clock Generator (ICG) Trim Value The internal clock generator (ICG) module is used to create a stable clock source for the microcontroller without using any external components. The untrimmed frequency of the low-frequency base clock (IBASE), will vary as much as ±25 percent due to process, temperature, and voltage dependencies. To compensate for these dependencies, an ICG trim value is located at address $FDC2. After trimming the ICG, a range of typ. ±2% (±3% max.) at nominal conditions (filtered (100nF) and stabilized (4,7uF) VDD = 5V, TAmbient~23°C) and will vary over-temperature and voltage (VDD) as indicated in the 68HC908EY16 data sheet. To trim the ICG, these values have to be copied to the ICG Trim Register ICGTR at address $38 of the MCU. Important The value has to be copied after every reset. OPERATING MODES OF THE MCU For a detailed description of the operating modes of the MCU, refer to the MC68HC908EY16 data sheet. Window closed no watchdog clear allowed Window open for watchdog clear WD timing x 50% WD timing x 50% WD period (PWD) WD timing selected by resistor on WDCONF terminal. (tPWD) |
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