MM908E624ACEWSLASHR2 datasheet(29/40 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

908E624

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI REGISTER OVERVIEW

Table 7 summarizes the SPI Register bit meaning, reset value, and bit reset condition.

SPI Control Register (Write)

Table 8 shows the SPI Control register bits by name.

LINSL2:1—LIN Baud Rate and Low-Power Mode

Selection Bits

These bits select the LIN slew rate and requested low-

power mode in accordance with Table 9. Reset clears the

LINSL2:1 bits.

LIN-PU—LIN Pullup Enable Bit

This bit controls the LIN pullup resistor during Sleep and

Stop modes.

• 1 = Pullup disconnected in Sleep and Stop modes.

• 0 = Pullup connected in Sleep and Stop modes.

In case the Pullup is disconnected a small current source

is used to pull the LIN terminal in recessive state. In case of

an erroneous short of the LIN bus to ground this will

significantly reduce the power consumption, e.g. in

combination with STOP/SLEEP mode.

HS3ON:HS1ON—High Side H3:HS1 Enable Bits

These bits enable the HSx. Reset clears the HSxON bit.

• 1 = HSx switched on (refer to Note below).

• 0 = HSx switched off.

Note

If no PWM on HS1 and HS2 is required, the PWMIN

terminal must be connected to the VDD terminal.

MODE2:1—Mode Section Bits

The MODE2:1 bits control the operating modes and the

watchdog in accordance with Table 10.

To safely enter Sleep or Stop mode and to ensure that

these modes are not affected by noise issue during SPI

transmission, the Sleep/Stop commands require two SPI

transmissions.

Table 7. SPI Register Overview

Read/Write

Information

Bit

Write

LINSL2

LINSL1

LIN-PU

HS3ON

HS2ON

HS1ON

MODE2

MODE1

Read

INTSRC (28)

LINWU

LINFAIL

HVF

LVF

BATFAIL (29)

VDDT

HSST

Write Reset Value

—

Write Reset Condition

POR,

RESET

POR,

RESET

POR

POR, RESET

POR,

RESET

POR,

RESET

——

Notes

28.

D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.

29.

The first SPI read after reset returns the BATFAIL flag state on bit D4.

Table 8. Control Bits Function (Write Operation)

LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1

Table 9. LIN Baud Rate and Low-Power Mode Selection

Bits

LINSL2

LINSL1

Description

Baud Rate up to 20 kbps (normal)

Baud Rate up to 10 kbps (slow)

Fast Program Download

Baud Rate up to 100 kbps

Low-Power Mode (Sleep or Stop) Request

Table 10. Mode Selection Bits

MODE2

MODE1

Description

Sleep Mode (30)

Stop Mode (30)

Watchdog Clear (31)

Run (Normal) Mode

Notes

30.

To enter Sleep and Stop mode, a special sequence of SPI

commands is implemented.

31.

The device stays in Run (Normal) mode.

MM908E624ACEW/R2 Datasheet(PDF) 29 Page - Freescale Semiconductor, Inc

MM908E624ACEW/R2 Datasheet(HTML) 29 Page - Freescale Semiconductor, Inc

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