MPC8315ECVRAGDA datasheet(100/112 Pages) FREESCALE

100 / 112 page

MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

100

Freescale Semiconductor

Clocking

24.2

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 76 shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in Table 76 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider has to be set properly so that the core VCO frequency is in the

range of 400–800 MHz.

24.3

Suggested PLL Configurations

To simplify the PLL configurations, the MPC8315E might be separated into two clock domains. The first

domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and

has the csb_clk as its input clock. The clock domains are independent, and each of their PLLs are

configured separately. Both of the domains has one common input clock. Table 77 shows suggested PLL

configurations for 33, 25, and 66 MHz input clocks.

Table 76. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider1

1 Core VCO frequency = core frequency × VCO divider.

0–1

2–5

0000

PLL bypassed

(PLL off,

csb_clk clocks core directly)

PLL bypassed

(PLL off,

csb_clk clocks core directly)

nnnn

nN/A

N/A

0001

01:1

0001

01:1

0001

11.5:1

0001

11.5:1

0010

02:1

0010

02:1

0010

12.5:1

0010

12.5:1

0011

03:1

0011

03:1

Table 77. Suggested PLL Configurations

Conf. No.

SPMF

Core\PLL

Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz)

0100

0000100

33.33

133.33

266.66

0100

0000101

100

250

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