MSC8102UG datasheet(76/80 Pages) FREESCALE

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MSC8102 Quad Core Digital Signal Processor, Rev. 12

4-4

Freescale Semiconductor

Design Considerations

• In single-master mode with the DLL disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is

set), the following connections should be used:

— Connect the oscillator output through a buffer to CLKIN.

— Connect DLLIN to GND (pull low).

— Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following

guidelines:

The maximum delay between the slave and CLKOUT must not exceed 0.7 ns.

The maximum load on CLKOUT must not exceed 10 pF.

Use a zero-delay buffer with a jitter less than 0.3 ns.

• If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, you can disconnect PPBS. Otherwise,

pull the signal up.

• The following signals: SWTE, DSISYNC, DSI64, MODCK[1–2], CNFGS, CHIPID[0–3], RSTCONF and BM[0–2] are used

to configure the MSC8102 and are sampled on the deassertion of the PORESET signal. Therefore, they should be

tied to GND or VDD either directly or through a pull-down or a pull-up resistor until the deassertion of the

PORESET

signal.

• You must pull up BR, BG, DBG, EXT_BR[2–3], EXT_BG[2–3], EXT_DBG[2–3], and TS if the BCR[EBM] bit is set.

• When they are used, you must pull up INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not

full drive).

Note:

For details on configuration, see the MSC8102 User’s Guide and MSC8102 Reference Manual.

4.3 Recommended Clock Connections for Single-Master

Mode with DLL Off

Use the guidelines shown in Figure 4-4 to connect CLKOUT to a slave device, such as an SDRAM. The zero-delay

buffer can use internal or external feedback.

Because the connection uses open loop timing between the internal and external clock (CLKOUT), the design must

adhere to the following requirements:

• The maximum delay between the CLKOUT pin to the SDRAM must be less than 0.7 ns.

• The maximum external load on CLKOUT must not exceed 10 pF.

• The zero-delay buffer must have a jitter of less than 0.3 ns.

Figure 4-4.

Example Clock Distribution In Single-Master Mode with DLL Disabled

Buffer

Zero-Delay

DLLIN CLKOUT

CLKIN

DLLDIS = 1

SDRAM

Buffer

Oscillator

MSC8102

MSC8102UG Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

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