MNSC140CORE datasheet(48/80 Pages) FREESCALE

48 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

2-18

Freescale Semiconductor

Specifications

2.5.7

TDM Timing

Table 2-18.

TDM Timing

Number

Characteristic

Expression

Minimum

Maximum

Units

300

TDMxRCLK/TDMxTCLK

TC1

—

301

TDMxRCLK/TDMxTCLK high pulse width

(0.5

± 0.1) × TC

—

302

TDMxRCLK/TDMxTCLK Low pulse width

(0.5

± 0.1) × TC

—

303

TDM receive all input set-up time

2.5

—

304

TDM receive all input hold time

2.5

—

305

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

active2,3

—

306

TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid2,3

—

307

All output hold time2

—

308

TDMxTCLK high to TDmXTDAT/TDMxRCLK output high

impedance

2,3

—

309

TDMxTCLK high to TDMXTSYN output valid

—

310

TDMxTSYN output hold time

3.9

—

Notes:

Values are based on a frequency range of 9–50 MHz.

Values are based on 30 pF capacitive load.

When configured as an output, TDMxRCLK acts as a second data link. See Chapter 22 of the

MSC8102 Reference Manual for

details.

Figure 2-13.

TDM Inputs Signals

Figure 2-14.

TDM Output Signals

TDMxRCLK

TDMxRDAT

TDMxRSYN

300

301

302

303

304

TDMxTCLK

TDMxTDAT

TDMxTSYN

305

306

308

307

300

301

302

310

309

TDMxRCLK

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