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ADSP-21469KBZ-ENG2 Datasheet(PDF) 34 Page - Analog Devices |
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ADSP-21469KBZ-ENG2 Datasheet(HTML) 34 Page - Analog Devices |
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34 / 56 page  Rev. PrB | Page 34 of 56 | November 2008 ADSP-21469/ADSP-21469W Preliminary Technical Data Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 30. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements tSFSE 1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) TBD TBD ns tHFSE 1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) TBD TBD ns tSDRE 1 Receive Data Setup Before Receive SCLK TBD TBD ns tHDRE 1 Receive Data Hold After SCLK TBD TBD ns tSCLKW SCLK Width TBD TBD ns tSCLK SCLK Period TBD TBD ns Switching Characteristics TBD TBD tDFSE 2 FS Delay After SCLK (Internally Generated FS in either Transmit or Receive Mode) TBD TBD ns tHOFSE 2 FS Hold After SCLK (Internally Generated FS in either Transmit or Receive Mode) TBD TBD ns tDDTE 2 Transmit Data Delay After Transmit SCLK TBD TBD ns tHDTE 2 Transmit Data Hold After Transmit SCLK TBD TBD ns 1 Referenced to sample edge. 2 Referenced to drive edge. Table 31. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements tSFSI 1 FS Setup Before SCLK (Externally Generated FS in either Transmit or Receive Mode) TBD TBD ns tHFSI 1 FS Hold After SCLK (Externally Generated FS in either Transmit or Receive Mode) TBD TBD ns tSDRI 1 Receive Data Setup Before SCLK TBD TBD ns tHDRI 1 Receive Data Hold After SCLK TBD TBD ns Switching Characteristics TBD TBD tDFSI 2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) TBD TBD ns tHOFSI 2 FS Hold After SCLK (Internally Generated FS in Transmit Mode) TBD TBD ns tDFSIR 2 FS Delay After SCLK (Internally Generated FS in Receive Mode) TBD TBD ns tHOFSIR 2 FS Hold After SCLK (Internally Generated FS in Receive Mode) TBD TBD ns tDDTI 2 Transmit Data Delay After SCLK TBD TBD ns tHDTI 2 Transmit Data Hold After SCLK TBD TBD ns tSCKLIW Transmit or Receive SCLK Width TBD TBD ns 1 Referenced to the sample edge. 2 Referenced to drive edge. |
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