ADSP-21469KBZ-ENG2 datasheet(37/56 Pages) AD

37 / 56 page

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 37 of 56

November 2008

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 34. IDP

signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1

pins using the SRU. Therefore, the timing specifications pro-

vided below are valid at the DAI_P20–1 pins.

Sample Rate Converter—Serial Input Port

The ASRC input signals (SCLK, FS, and SDATA) are routed

from the DAI_P20–1 pins using the SRU. Therefore, the timing

specifications provided in Table 35 are valid at the DAI_P20–1

pins.

Table 34. Input Data Port (IDP)

Parameter

Min

Max

Unit

Timing Requirements

tSISFS

FS Setup Before SCLK Rising Edge

TBD

tSIHFS

FS Hold After SCLK Rising Edge

TBD

tSISD

SData Setup Before SCLK Rising Edge

TBD

tSIHD

SData Hold After SCLK Rising Edge

TBD

tIDPCLKW

Clock Width

TBD

tIDPCLK

Clock Period

TBD

1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 24. IDP Master Timing

DAI_P20

-1

(SCLK)

DAI_P20

-1

(FS)

SAMPLE EDGE

tSISFS

tSIHFS

tIPDCLK

DAI_P20

-1

(SDATA)

tIPDCLKW

tSISD

tSIHD

Table 35. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

FS Setup Before SCLK Rising Edge

TBD

tSRCHFS

FS Hold After SCLK Rising Edge

TBD

tSRCSD

SDATA Setup Before SCLK Rising Edge

TBD

tSRCHD

SDATA Hold After SCLK Rising Edge

TBD

tSRCCLKW

Clock Width

TBD

tSRCCLK

Clock Period

TBD

1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

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