ADSP-BF504 datasheet(48/80 Pages) AD

48 / 80 page

Rev. PrC

Page 48 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

JTAG Test And Emulation Port Timing

Table 40 and Figure 29 describe JTAG port operations.

Table 40. JTAG Port Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

System Inputs Setup Before TCK High1

44ns

tHSYS

System Inputs Hold After TCK High

55ns

tTRSTW

TRST Pulse Width

2 (measured in TCK cycles)

TCK

Switching Characteristics

tDTDO

TDO Delay from TCK Low

tDSYS

System Outputs Delay After TCK Low3

12.6

1 System Inputs = SCL, SDA, PF15–0, PG15–0, PH2–0, NMI, BMODE3–0, RESET, PG.

2 50 MHz Maximum

3 System Outputs = EXTCLK, SCL, SDA, PF15–0, PG15–0, PH2–0.

Figure 29. JTAG Port Timing

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

ADSP-BF504 Datasheet(PDF) 48 Page - Analog Devices

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