MPC8377E datasheet(48/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

11.2.2.2

Full-Speed Read Meeting Hold (Minimum Delay)

There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.

tCLK_DELAY + tOH + tDATA_DELAY > tSFSIXKH

Eqn. 9

This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.

11.3

eSDHC AC Timing Specifications (High-Speed Mode)

Table 43 provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and

Figure 31.

Table 43. eSDHC AC Timing Specifications for High-Speed Mode

At recommended operating conditions OVDD = 3.3 V ± 165 mV.

Parameter

Symbol1

Min

Max

Unit

Notes

SD_CLK clock frequency—high speed mode

fSHSCK

050

MHz

—

SD_CLK clock cycle

tSFSCK

—

SD_CLK clock frequency—identification mode

fSIDCK

0400

KHz

—

SD_CLK clock low time

tSHSCKL

7—

SD_CLK clock high time

tSHSCKH

7—

SD_CLK clock rise and fall times

tSHSCKR/

tSHSCKF

—3

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

tSHSIVKH

5—

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

tSHSIXKH

0—

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

tSHSKHOV

—4

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid

tSHSKHOX

0—

SD_CLK delay within device

tINT_CLK_DLY

1.5

—

SD Card Input Setup

tISU

6—

SD Card Input Hold

tIH

2—

SD Card Output Valid

tODLY

—14

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