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PCF2119RU2DB2 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCF2119RU2DB2 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 83 page ![]() PCF2119X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 7 — 15 November 2010 9 of 83 NXP Semiconductors PCF2119x LCD controllers/drivers [1] The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software (see Table 43 and Table 44). 8.3 Power-down mode The chip can be put into power-down mode by applying a HIGH-level to pin PD. In power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAM and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked. Table 4. State after reset Step Function Control bit and register state Description Reference 1 Clear_display Table 16 2 Entry_mode_set bit I_D = 1 incremental cursor move direction Table 18 bit S = 0 no display shift 3 Display_ctl bit D = 0 display off Table 19 bit C = 0 cursor off bit B = 0 cursor character blink off 4 Function_set bit DL = 1 8-bit interface Table 12 bit M = 0 1-line display bit SL = 0 1:18 multiplex drive mode bit H = 0 normal instruction set 5 default address pointer to DDRAM [1] Table 22 6 Icon_ctl bit IM = 0 character mode, full display Table 25 bit IB = 0 icon blink disabled 7 Screen_conf bit L = 0 default configuration Table 23 Disp_conf bit P = 0; bit Q = 0 default configurations Table 24 8 Temp_ctl bit TC1 = 0; bit TC2 = 0 default temperature coefficient Table 28 9 VLCD_set register VA =0; register VB =0 VLCD generator off Table 32 10 I2C-bus interface reset 11 HV_gen bit S1 = 1; bit S0 = 0 VLCD generator set to 3 internal stages (4 voltage multipliers) Table 30 |
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