APPLICATIONS

Setting output voltage

When connected as shown in the typical application

circuit, the ZXLD1601 will produce a nominal default

output of between 26V and 28V. This is set by the

internal potential divider comprising of resistors R1

and R2. (See device block diagram).

The internal potential divider network R1/R2 is

accessible at the FB pin and can be shunted by means

of external resistors to set different nominal output

voltages. The potential divider defines output voltage

according to the relationship:

VV

R

R

OUT

FB

=+

⎛

⎝

⎜

⎞

⎠

⎟

1

2

1

where VFB = 1.025V.

When using external resistors, these should be chosen

with lower values than the internal resistors to

minimize errors caused by the device to device

variation in absolute value of the internal resistors

(

±30% max). The internal resistors have high values in

order to minimize these errors.

The following table gives suggested values for various

output voltages.

Once the nominal output voltage has been set, it can be

adjusted to a lower value by applying a pulse width

modulated (PWM) control signal to the EN pin, using

one of the two methods described below.

PWM adjustment permits the device to be turned on

and the output voltage set by a single logic signal

applied to the EN pin. No external resistors are

required and the amplitude of the control signal is not

critical, providing it conforms to the limits defined in

the electrical characteristics.

1) PWM output voltage adjustment (analogue mode)

During this mode of operation the device operation is

continuous, providing a low ripple output voltage

logic signal applied to the EN pin according to the

relationship:

Square wave signals applied to the EN pin, for

example, will turn the device on and produce a nominal

regulated output of 13.5V.

The ZXLD1601 contains a timing circuit that switches

the device on a few microseconds after the application

of a rising edge to EN and turns it back off again

nominally 120

µs after the falling edge of EN. For

continuous PWM mode operation, the frequency of the

control signal must therefore be maintained above

10kHz at all times, to prevent the internal delay circuit

from timing out and switching the device into standby

mode. The maximum frequency applied to EN should

be limited to 100kHz to minimize errors due to internal

switching delays

2) PWM output voltage adjustment (gated mode)

This method of adjustment can be used in applications

where the output ripple is less important than the

supply current. The method of adjustment is the same

as in 1) above, however, during this mode of operation,

the device is gated on and off, providing an average

cycle (D) of the logic signal applied to the EN pin

according to the relationship:

The ripple on this voltage will be determined by the size

of the output capacitor.

The output voltage can be adjusted all the way down to

the input voltage by either method of PWM control, but

for best results, the duty cycle range should be kept

within the specified range. Lower duty cycles will result

in increased output ripple and non-linearity in the

relationship between duty cycle and output voltage. If a

greater control range is required, the nominal output

can be reduced by the use of external resistors before

the PWM signal is applied.

Minimizing output voltage ripple

For applications requiring lower output ripple it may be

necessary to add a small ceramic capacitor in parallel

with R2. A value of 4.7pF is suitable for most output

ranges.

ZXLD1601

SEMICO NDUC TORS

ISSUE 3 - AUGUST 2004

8

Required

output voltage

External

resistor across

R1

External resistor

across R2

5V

43K

130K

12V

56K

487K

18V

43K

649K

21V

34.8K

649K

25V

27K

620K

28V

40.2K

1.07M