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LC72P366 Datasheet(PDF) 13 Page - Sanyo Semicon Device |
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LC72P366 Datasheet(HTML) 13 Page - Sanyo Semicon Device |
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13 / 14 page  No. 5544-13/14 LC72P366 Continued from preceding page. Mnemonic Operand Function Operation Machine code 1st 2n D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 AND r M AND M with r r ← (r) AND (M) 0 0 1 0 0 0 DH DL r ANDI M I AND I with M M ← (M) AND I 0 0 1 0 0 1 DH DL I OR r M OR M with r r ← (r) OR (M) 0 0 1 0 1 0 DH DL r ORI M I OR I with M M ← (M) OR I 0 0 1 0 1 1 DH DL r EXL r M Exclusive OR I with r r ← (r) XOR I 0 0 1 1 0 1 DH DL r EXLI M I Exclusive OR I with M M ← (M) XOR I 0 0 1 1 0 1 DH DL I SHR r Shift r right with carry carry 0 0 0 0 0 0 0 0 1 1 1 0 r (r) LD r M Load M to r r ← (M) 1 1 0 1 0 0 DH DL r ST M r Store r to M M ← (r) 1 1 0 1 0 1 DH DL r MVRD r M Move M to destinsation [DH, rn] ← (M) 1 1 0 1 1 0 DH DL r M referring to r in the same row MVRS M r Move M to destinsation M ← [DH, rn] 1 1 0 1 1 1 DH DL r M referring to r in the same row MVSR M1 M2 Move source M referring [DH, DL1] ← [DH, DL2] 1 1 1 0 0 0 DH DL1 DL2 to r to M in the same row MVI M I Move I to M M ← I 1 1 1 0 0 1 DH DL I TMT M N Test M bits, then skip if M (N) = all “1”, 1 1 1 1 0 0 DH DL N if all bits specified then skip are true TMF M N Test M bits, then skip if M (N) = all “0”, 1 1 1 1 0 1 DH DL N if all bits specified then skip are false JMP ADDR Jump to the address PC ← ADDR 1 0 ADDR (14 bits) CAL ADDR Call subroutine Stack ← (PC) + 1 1 1 0 0 ADDR (12 bits) RT Return from subroutine PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 0 RTS Return from subroutine PC ← Stack + 1 0 0 0 0 0 0 0 0 1 0 1 0 and skip RTB Return from subroutine PC ← Stack 1 1 1 1 1 1 1 1 1 1 0 0 with bank data BANK ← Stack RTBS Return from subroutine PC ← Stack + 1 1 1 1 1 1 1 1 1 1 1 0 1 with bank data and skip BANK ← Stack RTI Return from interrupt PC ← Stack 0 0 0 0 0 0 0 0 1 0 0 1 BANK ← Stack CARRY ← Stack SS I N Set status register (Status reg I) N ← 1 1 1 1 1 1 1 1 1 0 0 0 I N RS I N Reset status register (Status reg I) N ← 0 1 1 1 1 1 1 1 1 0 0 1 I N TST I N Test status register if (Status reg I) N = 1 1 1 1 1 1 1 1 0 1 I N true all “1”, then skip TSF I N Test status register if (Status reg I) N = 1 1 1 1 1 1 1 1 1 0 I N false “0”, then skip TUL N Test unlock F/F then if Unlock FF (N) = 0 0 0 0 0 0 0 0 1 1 0 1 N skip if it has not been all “0”, then skip set PLL M r Load M to PLL register PLL reg ← PLL data 1 1 1 1 1 0 DH DL r INR M Rn Input register/port M ← (Rn reg) 0 0 1 1 1 0 DH DL Rn data to M OUTR M Rn Output contents of M Rn reg ← (M) 0 0 1 1 1 1 DH DL Rn to register/port Continued on next page. |
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