HT66F13 datasheet(113/173 Pages) HOLTEK

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ACERL Register

Bit

76543210

Name

¾¾¾¾

ACE3

ACE2

ACE1

ACE0

R/W

¾¾¾¾

R/W

POR

¾¾¾¾

1111

Bit 7~4

unimplemented, read as

²0²

Bit 3

ACE3: Define PA3 is A/D input or not

0: Not A/D input

1: A/D input, AN3

Bit 2

ACE2: Define PA2 is A/D input or not

0: Not A/D input

1: A/D input, AN2

Bit 1

ACE1: Define PA1 is A/D input or not

0: Not A/D input

1: A/D input, AN1

Bit 0

ACE0: Define PA0 is A/D input or not

0: Not A/D input

1: A/D input, AN0

A/D Operation

The START bit in the ADCR0 register is used to start and reset the A/D converter. When the

microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle

will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in

the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit

that is used to control the overall start operation of the internal analog to digital converter.

The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process

is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has

ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control

This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt

address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll

the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of

detecting the end of an A/D conversion cycle.

The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to

be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the

ADCK2~ADCK0 bits in the ADCR1 register.

Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0,

there are some limitations on the maximum A/D clock source speed that can be selected. As the

minimum value of permissible A/D clock period, tADCK,is0.5

ms, care must be taken for system clock

frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of

4MHz, the ADCK2~ADCK0 bits should not be set to 000B. Doing so will give A/D clock periods that

are less than the minimum A/D clock period which may result in inaccurate A/D conversion values.

Refer to the following table for examples, where values marked with an asterisk * show where,

depending upon the device, special care must be taken, as the values may be less than the specified

minimum A/D Clock Period.

Rev. 1.10

113

February 9, 2011

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

HT66F13 Datasheet(PDF) 113 Page - Holtek Semiconductor Inc

HT66F13 Datasheet(HTML) 113 Page - Holtek Semiconductor Inc

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