LC07424LP

No.A1619-16/32

Register Description (Note) This section deals with the outline. Be sure to confirm the description here by referring to

the page dealing with the detailed explanation.

ADRS

Bit

Name

INIT

Description

[7]

00b

Setting the common reference voltage circuit

[6]

VREF_BIAS

11: Normal operation 10: Rapid charging 01: pull-down 00: Power down

[5]

SYNC_CLR

0b

Digital block synchronous reset control

1: Reset

0: Norma l: operation

[4]

SEL_PDX

0b

Selector block power DOWN

1: Normal operation

0: Power down

[3]

ALC_PDX

0b

ALC block power down

1: Normal operation

0: Power down

[2]

ADC_A_PDX

0b

ADC Analog block power down

1: Normal operation

0: Power down

[1]

DAC_A_PDX

0b

DAC Analog block power down

1: Normal operation

0: Power down

00h

[0]

VIDEO_PDX

0b

VIDEO power down

1: Normal operation

0: Power down

[7]

SP_OUTEN

0b

Speaker out enable

0: Speaker output stop

1: Normal operation

[6]

SP_PDX

0b

Speaker power down

1: Normal operation

0: Power down

[5]

MIX_PDX

0b

MIX Power down

1: Normal operation

0: Power down

[4]

0

0b

0: Fixed

[3]

LO_PDX

0b

Line out power down

1: Normal operation

0: Power down

[2]

ADC_D_PDX

0b

ADC logic block power down

1: Normal operation

0: Power down

[1]

DAC_D_PDX

0b

DAC logic block power down

1: Normal operation

0: Power down

01h

[0]

SP_EVR_PDX

0b

Speaker EVR power down 1: Normal operation 0: Fixed at [SP_GAIN]=00h

[7]

0

0b

0: Fixed

[6]

0

0b

0: Fixed

[5]

0

0b

0: Fixed

[4]

ADC_LIN_L

1b

Lch line Input selection 0: Non-selection 1: Selection

[3]

0

0b

0: Fixed

[2]

0

0b

0: Fixed

[1]

0

0b

0: Fixed

02h

[0]

ADC_LIN_R

1b

Rch line Input selection 0: Non-selection 1: Selection

[7]

[6]

[5]

ALC_VAL

001b

ALC circuit, ALC value (limiter level) setting

111:-10dBFS 110: -9dBFS 101: -8dBFS 100: -7dBFS

011: -6dBFS 010: -5dBFS 001: -4dBFS 000: -3dBFS

[4]

[3]

ALC_FA

11b

ALC circuit, Attack factor setting

11: (1 / 8)dB 10: (1 / 4)dB 01: (1 / 2)dB 00: (1 / 1)dB

[2]

[1]

03h

[0]

ALC_FR

101b

ALC circuit, Recovery factor setting

111: (1 / 2^14)dB 110: (1 / 2^13)dB 101: (1 / 2^12)dB 100: (1 / 2^11)dB

011: (1 / 2^10)dB 010: (1 / 2^9)dB 001: (1 / 2^8)dB 000: (1 / 2^7)dB

[7]

ALC_ZCD

1b

ALC circuit, Gain change in the zero cross timing 1: ON 0: OFF

[6]

[5]

ALC_ZCDTM

00b

ALC circuit, Timeout time setting at detection of zero cross

11: 8192 (1 / fs) 10: 4096 (1 / fs) 01: 2048 (1 / fs) 00: 1024 (1 / fs)

[4]

ALC_FULLEN

0b

ALC circuit, Full-scale detection operation setting

1: ON 0: OFF

[3]

[2]

ALC_ATLIM

01b

ALC circuit, Limit setting for attach operation frequency between zero crosses

11: 16 回 10: 8 回 01: 4 回 00: 2 回

[1]

04h

[0]

ALC_RWT

10b

ALC circuit, standby time setting during recovery operation

11: 2048 (1 / fs) 10: 1024 (1 / fs) 01: 512 (1 / fs) 00: 256 (1 / fs)

[7]

ALC_OFF

0b

ALC circuit

1: ALC function OFF (Manual mode) 0: ALC function ON

[6]

[5]

[4]

[3]

[2]

[1]

05h

[0]

ALC_VMAX

1Ch

ALC circuit, Maximum gain value setting of PGA when the ALC function is ON

7Fh to 61h: Set prohibition

60h: +34dB

to 0.5dB step

1Ch: 0dB

to 0.5dB step

00h: -14dB