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LC07424LP Datasheet(PDF) 22 Page - Sanyo Semicon Device |
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LC07424LP Datasheet(HTML) 22 Page - Sanyo Semicon Device |
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22 / 32 page  LC07424LP No.A1619-22/32 ADRS Bit Name INIT Description [7] ALC_ZCD 1b ALC circuit, Gain change in the zero cross timing 1: Gain changed in the zero cross timing 0: Gain changed without waiting for zero cross timing [6:5] ALC_ZCDTM[1:0] 00b ALC circuit, Time setting for timeout at zero cross detection Effective when [ALC_ZCD]=1 11: 8192 (1 / fs) 10: 4096 (1 / fs) 01: 2048 (1 / fs) 00: 1024 (1 / fs) [4] ALC_FULLEN 0b ALC circuit, Full scale detection operation setting Rapid level down at detection of full scale 1: ON 0: OFF [3:2] ALC_ATLIM[1:0] 01b ALC circuit, Limit setting for the attack operation frequency between zero crosses effective when [ALC_ZCD]=1. For the actual reduction for the frequency, See Table 1. 11: 16 回 10: 8 回 01: 4 回 00: 2 回 04h [1:0] ALC_RWT[1:0] 10b ALC circuit, Standby time setting during recovery operation. 11: 2048 (1 / fs) 10: 1024 (1 / fs) 01: 512 (1 / fs) 00: 256 (1 / fs) [7] ALC_OFF 0b ALC circuit, Operation stop 1: Operation stop (manual mode) [ALC_DVL] and [ALC_DVR] become effective. 0: Normal operation 05h [6:0] ALC_VMAX[6:0] 1Ch ALC circuit, PGA maximum gain value setting during ALC operation See Table 8.2. [7] ALC_MUTE_L 0b ALC circuit, PGA MUTE setting (Lch) 1: ON 0: OFF 06h [6:0] ALC_DVL[6:0] 1Ch ALC circuit, Lch PGA gain value setting in the manual mode See Table 8.2. [7] ALC_MUTE_R 0b ALC circuit, PGA MUTE setting (Rch) 1: ON 0: OFF 07h [6:0] ALC_DVR[6:0] 1Ch ALC circuit, Rch PGA gain value setting in the manual mode See Table 8.2. Refer to "Description of ALC operation." Table 8.1. "Reduction value for the set frequency" [ALC_FA] [ALC_ATLIM] No, of times 11b 10b 01b 00b 11b 16 2 dB 4 dB 8 dB 16 dB 10b 8 1 dB 2 dB 4 dB 8 dB 01b 4 0.5 dB 1 dB 2 dB 4 dB 00b 2 0.25 dB 0.5 dB 1 dB 2 dB |
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