LC07424LP

Checkpoints

!! The user is responsible for ascertaining whether this IC can be adopted for the mass production sets, including the various

conditions for mounting in the set.

Power supply

• Powr pins are 4.8V, 2.8V, and 1.8V systems.

4.8V system: Analog power supplies (VDDh, VDDvh)

2.8V system: Analog power supplies (VDDana, VDDsp, VDDv)

1.8V system: Digital powr supply (VDDdig), digital IO power supply (VDDio)

Connect the decoupling capacitor near the power pin. Refer to our reference substrate data.

• Power ON

Simultaneous rise and fall while maintaining the voltage sequence.

Alternatively, raise starting from the higher voltage (4.8 V system) side and fall starting from the low voltage (1.8 V system) side.

The voltage sequence is 4.8V system ≥ 2.8V system ≥ 1.8V system.

Register control

• Set data for all registers including those for the test. Refer to our recommended register data file.

• Registers designated as "registers for LSI test" are fixed at the initial value (INIT).

Resetting

• When power has been applied, be sure to reset.

(A) or (B) is executed as shown in the figure below.

(A) is reset at the same time as the power is first applied.

(B) is reset immediately after the power is first applied.

The circuit state is uncertain if the reset is not made. It is recommended to set "th" as short as possible.

The RESET_X pin input circuit is subject to clock synchronizing processing.

Accordingly, the MCLK pin clock input is always necessary even during periods (A) and (B).

tD

0.2VDDio

Clock ON

RESET_X

MCLK

tH

tD

0.2VDDio

Clock ON

RESET_X

MCLK

(A)

(B)

95% power startup level

Normal operation

Power pin

No.A1619-31/32