 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
16F1827 Datasheet(PDF) 94 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
16F1827 Datasheet(HTML) 94 Page - Microchip Technology |
|
|
94 / 406 page  PIC16(L)F1826/27 DS41391D-page 94 2011 Microchip Technology Inc. 8.6.9 PIR4 REGISTER(1) The PIR4 register contains the interrupt flag bits, as shown in Register 8-9. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Note 1: The PIR4 register is available only on the PIC16(L)F1827 device. 2: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 8-9: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 — — — — — — BCL2IF SSP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware bit 7-2 Unimplemented: Read as ‘0’ bit 1 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A Bus Collision was detected (must be cleared in software) 0 = No Bus collision was detected bit 0 SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit 1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software) 0 = Waiting to Transmit/Receive/Bus Condition in progress Note 1: This register is only available on PIC16(L)F1827. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 86 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 177 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 87 PIE2 OSFIE C2IE C1IE EEIE BCL1IE — — CCP2IE(1) 88 PIE3(1) — — CCP4IE CCP3IE TMR6IE —TMR4IE —89 PIE4(1) — — — — — — BCL2IE SSP2IE 90 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 91 PIR2 OSFIF C2IF C1IF EEIF BCL1IF — —CCP2IF(1) 92 PIR3(1) — — CCP4IF CCP3IF TMR6IF —TMR4IF —93 PIR4(1) — — — — — — BCL2IF SSP2IF 94 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Note 1: PIC16(L)F1827 only. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
