IMX28CEC datasheet(32/70 Pages) FREESCALE

32 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

3.5.3.2

DDR Output AC Timing

Figure 6 and Table 36 show the DDR output AC timing defined for all DDR types: LPDDR1, standard

DDR2 (1.8 V), and LVDDR2 (1.5 V)

Figure 6. DDR Output AC Timing

DDR3

CK low level width

tCL

0.5 tCK

–0.5

0.5 tCK

+ 0.5

DDR4

Address and control output setup time

tIS

0.5 tCK – 1

0.5 tCK

+ 0.5

DDR5

Address and control output hold time

tIH

0.5 tCK – 1

0.5 tCK

+ 0.5

Table 36. DDR Output AC Timing

Description

Symbol

Min

Max

Unit

DDR10

Positive DQS latching edge to associated CK edge

tDQSS

–0.5

0.5

DDR11

DQS falling edge from CK rising edge—hold time

tDSH

0.5 tCK

–0.5

0.5 tCK

+ 0.5

DDR12

DQS falling edge to CK rising edge—setup time

tDSS

0.5 tCK

–0.5

0.5 tCK

+ 0.5

Table 35. EMI Command/Address AC Timing (continued)

Description

Symbol

Min.

Max.

Unit

EMI_CLK

EMI_CLKN

EMI_DQS

DDR13

DDR14

DDR10

EMI_DQ & EMI_DQM

DDR11

DDR12

DDR15

DDR16

EMI_DQSN

IMX28CEC Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

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