IMX28CEC datasheet(37/70 Pages) FREESCALE

37 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

3.5.4.1.4

MII Serial Management Channel Timing (ENET0_MDIO and ENET0_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3

MII specification. However the ENET can function correctly with a maximum MDC frequency of

15 MHz.

Figure 12 shows MII asynchronous input timings. Table 42 describes the timing parameters (M10–M15)

shown in the figure.

Figure 12. MII Serial Management Channel Timing Diagram

3.5.4.2

RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference

clock. ENET0_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include

ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER.

Table 42. MII Serial Management Channel Timing

Characteristic

Min.

Max.

Unit

M10

ENET0_MDC falling edge to ENET0_MDIO output invalid (min.

propagation delay)

0—

M11

ENET0_MDC falling edge to ENET0_MDIO output valid (max.

propagation delay)

—5

M12

ENET0_MDIO (input) to ENET0_MDC rising edge setup

—

M13

ENET0_MDIO (input) to ENET0_MDC rising edge hold

—

M14

ENET0_MDC pulse width high

40%

60%

ENET0_MDC period

M15

ENET0_MDC pulse width low

40%

60%

ENET0_MDC period

ENET0_MDC (output)

ENET0_MDIO (output)

M14

M15

M10

M11

M12

M13

ENET0_MDIO (input)

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