TLE7239SL datasheet(12/37 Pages) INFINEON

12 / 37 page

Data Sheet

Rev. 1.0, 2010-02-18

SPI Driver for Enhanced Relay Control

TLE7239SL

Electrical Characteristics

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards.

For more information, go to www.jedec.org.

Thermal Resistance1)

1) Not subject to production test

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

4.3.1

Junction to Case, bottom

thJC,back

––

K/W

2) Specified

thJSP value is simulated at natural convection on a cold plate setup (all pins are fixed to ambient temperature).

a = 85 °C. Ch1 to Ch8 are dissipating 1 W power (0.125 W each).

4.3.2

Junction to Case, top

thJC,top

––

K/W

4.3.3

Junction to Pin (1,2,11 or 12)

thJPin

––

K/W

4.3.4

Junction to Ambient

(1s0p, min. footprint)

thJA,min

–90

–

K/W

3) Specified

thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with minimal footprint copper area and 70

µm thickness.

Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).

4.3.5

Junction to Ambient

(1s0p+300mm2Cu)

thJA,300

–70

–K/W

4) Specified

thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 300mm2

and 70

µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).

4.3.6

Junction to Ambient

(1s0p+600mm2Cu)

thJA,600

–65

–K/W

5) Specified

thJA value is according to Jedec JESD51-2,-3 at natural convection on FR4 1s0p board; The product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with additional heatspreading copper area of 600mm2

and 70

µm thickness. Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).

4.3.7

Junction to Ambient (2s2p)

thJA,2s2p

–55

–K/W

6) Specified

thJA value is according to Jedec JESD51-2,-7 at natural convection on FR4 2s2p board; The product

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70

µm Cu, 2 x 35 µm Cu).

Ta = 85 °C, Ch1 to Ch8 are dissipating 1 W power (0.125 W each).

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