PCF8576C datasheet(10/57 Pages) NXP

10 / 57 page

PCF8576C

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Product data sheet

Rev. 10 — 22 July 2010

10 of 57

NXP Semiconductors

PCF8576C

Universal LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8576C.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.

7.1 Power-On-Reset (POR)

At power-on the PCF8576C resets to the following starting conditions:

• All backplane and segment outputs are set to VDD

• The selected drive mode is 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• Input and output bank selectors are reset (as defined in Table 8)

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be

temperature compensated externally through the VLCD supply to pin VLCD.

Fractional LCD biasing voltages are obtained from an internal voltage divider comprising

three series resistors connected between VDD and VLCD. The center resistor can be

switched out of the circuit to provide a 1

⁄

2 bias voltage level for the 1:2 multiplex

configuration.

Fig 7.

Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

≤

2CB

SDA

SCL

OSC

40 segment drives

4 backplanes

LCD PANEL

(up to 160

elements)

PCF8576C

SA0 V

VSS

VDD

LCD

013aaa098

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